The present invention relates to semiconductor memory device and, more specifically, to tests for detecting margin deficiencies in the capacity of capacitors or the like constituting each memory cell of a dynamic RAM (Random Access Memory) of the shared sense amplifier system.
There are some cases where the operating margin of some part within a dynamic RAM (DRAM) decreases due to abnormalities in the memory cell array or its peripheries of the DRAM, resulting in unstable operation such that the DRAM will not operate in compliance with specifications. Margin deficiencies that may cause faults of this kind include:
(1) deficiency memory cell storage capacitance (hereinafter, referred to as "cell capacitance margin deficiency"); PA1 (2) deficiency of sense amplifier sensitivity (hereinafter, referred to as "sense margin deficiency"); PA1 (3) deficiency of sense operation sensitivity due to a preamplifier of an intermediate buffer connected to local I/O lines i.e. signal lines for transmitting to another section (intermediate buffer) within the DRAM a data signal which is obtained after data is read from memory cells and the sense amplifier is activated (hereinafter, referred to as "local I/O sense margin deficiency"); PA1 (4) deficiency of the ability to reliably and correctly write data into memory cells (hereinafter, referred to as "write margin deficiency"); and PA1 (5) deficiency of the ability of precharge a bit line pair to Vcc/2 (where Vcc is the power supply voltage) before reading data from the memory cells or other operations (hereinafter, referred to as "equalize margin deficiency").
Faults due to such margin deficiencies as described above must be detected in tests. However, the tests for detecting such faults take a long time, while the number of bits in DRAMs has been increasing. As a result, there has been a demand for speeding up the tests for detecting faults due to margin deficiencies.
Under these circumstances, Japanese Patent Laid-Open Publications HEI 3-137889 and HEI 4-216400 have disclosed a margin evaluation method or a semiconductor memory which is enabled to evaluate the margin of storage capacitance of memory cells or to detect a cell capacitance margin deficiency by the bit line capacitance being increased in the test mode by connecting not only a bit line pair which would be connected in normal operation but also a bit line pair which would not be connected, to the sense amplifier, in a DRAM by the shared sense amplifier system which allows two or more bit line pairs to be connected to one sense amplifier. Such a method and equipment make it possible to speed up the tests for detecting faults due to cell capacitance margin deficiency. The Japanese Patent Laid-Open Publication HEI 4-216400 corresponds to the U.S. Pat. No. 5,339,273 incorporated herein by reference.
The margin evaluation method or the semiconductor memory disclosed in the above publications is indeed capable of detecting faults due to cell capacitance margin deficiency, but is incapable of detecting faults due to the margin deficiencies as described in (2) to (4) above. Also, in the semiconductor memory or test methods therefor disclosed in Japanese Patent Laid-Open Publication HEI 3-137889, a bit line pair which would not be connected in normal operation among a plurality of bit line pairs that can be connected to one sense amplifier is connected to the sense amplifier in the test mode after a word line from which data is to be read is selected. In this case, noise due to the connection of the bit line pair that would not be connected to the sense amplifier in normal operation would affect the test operation. As a result, when such a test has resulted in a decision of a fault, the cause of the fault can not be distinguished between a cell margin deficiency and a noise margin deficiency, which leads to a possibility that the cause of the fault can not be determined completely.